1. Field of the Invention
The invention relates to a circuit arrangement for recovering a clock frequency.
2. Description of the Related Art
A circuit arrangement of this type is necessary, for example, in clock recovery circuits for digital transmission networks in communication and data technology, if from a digital input signal a specific clock frequency is to be regenerated. In a digital transmission network in accordance with G 703 (CCITT=CommiteConsultatif International Telegraphique et Telephonique) a 64 kbit/s data signal or a 64 kHz clock signal can be used for recovering the clock frequency. If the clock signal is used for recovering the clock frequency, the frequency of the clock signal can be converted into the desired clock frequency, for example, by means of a clock divider. If the data signal is used for recovering the clock frequency, it should be taken into account that the data signal often does not contain the desired clock frequency. A data signal according to G 703 (CCITT) is, for example, represented as a ternary data signal which is based on a binary information signal encoded in five steps. In this case integrated switching circuits may be used for recovering the clock frequency from the ternary data signal, which circuits are based on a decoding of said code conversion. These circuits, however, represent a considerable cost factor.